发明名称 |
Semiconductor device |
摘要 |
<p>A PMOS 21 and an NMOS 22, which are connected in series between a power supply potential Vcc and a ground potential Vss, perform ON and Off operation in accordance with data signals G1 and G2 from an output buffer control circuit 40, and generate an output signal. A Vpp generating circuit 50 generates a potential Vpp higher than the power supply potential Vcc and a back gate bias of the PMOS 21 is set at the potential Vpp. Even if a latch-up trigger current due to a surge voltage is produced, the back gate bias of the PMOS 21 is set at Vpp and therefore a potential difference caused in an N type well resistor becomes small and a base potential of a parasitic bipolar transistor disposed between the N type well 2 and a substrate 1 becomes approximate to the potential Vpp. Accordingly, the current which flows into the substrate 1 is suppressed and a latch-up tolerance is improved. <IMAGE></p> |
申请公布号 |
EP0720295(A2) |
申请公布日期 |
1996.07.03 |
申请号 |
EP19950119653 |
申请日期 |
1995.12.13 |
申请人 |
OKI ELECTRIC INDUSTRY COMPANY, LIMITED |
发明人 |
ISHIMURA, TAMIHIRO;MIYAMOTO, SAMPEI |
分类号 |
G11C11/413;G11C11/408;G11C11/409;H01L21/822;H01L27/04;H01L27/08;H01L27/092;H03K17/08;H03K17/687;H03K19/003;H03K19/0175;H03K19/0948;(IPC1-7):H03K19/003 |
主分类号 |
G11C11/413 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|