| 摘要 |
<p>In a multi-level DRAM, one of multiple voltage levels may be stored in each memory cell. In a four-level system, each of a pair of bitlines is divided into two subbitlines which are connected to respective sense amplifiers. Dummy cells matching the storage cell are provided on each subbitline to balance the capacitances of the subbitlines. The stored voltage is dumped onto left and right subbitlines which are then isolated, and one of the voltages is then sensed to provide a sign bit. A second reference level is generated by dumping the charge associated with the sign bit over three subbitlines and the magnitude bit is sensed using that reference. The stored voltage is restored by charge sharing a sign bit charge on two bitlines with a magnitude bit charge on one bitline.</p> |
