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发明名称
METHOD FOR CONFIGURATION AND DESIGNING OF VLSI CIRCUIT
摘要
申请公布号
JPH08171576(A)
申请公布日期
1996.07.02
申请号
JP19940170629
申请日期
1994.07.22
申请人
NEC CORP;RAJIYAAZU THE STATE UNIV OF NIYUUJIYAAG;AT & T CORP
发明人
SURIMATSUTO TEII CHIYARADAHAA;SHIYUUMAN KANJIRARU;BISHIYUWANI AGURAWARU
分类号
G06F17/50;G01R31/3183;(IPC1-7):G06F17/50
主分类号
G06F17/50
代理机构
代理人
主权项
地址
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