| 摘要 |
PURPOSE: To efficiently activate and end threads in a multithread processor. CONSTITUTION: This processor is constituted of an instruction pipeline device 140 and a register file device 120 and the register file device 120 is constituted of plural register banks 130. The register file device 120 and an external memory device 190 are connected through a register frame loading/storing line 121 and register frames defined as the stored contents of the register banks 130 are loaded and stored altogether. The register frames are saved through the loading/storing line 121 at the time of executing a thread parallel activation instruction and a thread successive activation instruction and the register frames are recovered through the loading/storing line 121 at the time of executing a thread end instruction and a thread return instruction. |
