CONTROLLING METHOD FOR COUNTER IN CLOCK GENERATION CIRCUIT

摘要

PURPOSE: To stably generate a reference clock regardless of switching from the current system to the standby system. CONSTITUTION: The phase difference between frequency divided clocks REF0 and REF1 is detected by a phase difference detection circuit 12, and it is detected whether this phase difference is 1.5 times as long as the clock width of a system 0 clock CLK0 (CLK1) or longer. Only when it is 1.5 times as long as this clock width or longer, a load signal 1d0 (ld1) is outputted to a frequency division counter 1-0 (1-1) of the standby system clock. The load signal 1d0 (ld1) is loaded by the frequency division counter 1-0 (1-1) to divide the frequency of the system 0 (system 1) clock CLK0 (CLK1), and a frequency divided clock REF0 (REF1) is outputted. The frequency divided clock REF0 (REF1) is selected in accordance with a clock system select signal ACT by a selector 2, and a reference clock REF is outputted to a phase locked loop circuit 4.