PACKET PHASE SYNCHRONIZING CIRCUIT

摘要

PURPOSE: To reduce a capacity and delay of a memory to be used for phase synchronization and to improve the performance of a communication equipment by performing a phase synchronization for every packet and inserting a specified fixed length packet between the packets at the time of processing the packets. CONSTITUTION: A writing control circuit 102 takes out the packets of a payload area and successively writes the packets in a first in/first out memory (FIFO) 101. A reading control circuit 103 takes out and reads each line phase synchronization for every packet of the packets stored within the memory 101. At the time of a packet reading, overhead is eliminated and phase synchronizations are performed for plural first fixed length packets by a packet unit. A uniform length second fixed length packet is inserted, and first and second fixed length packets are outputted in conformity with the phase and the signal format within a communication equipment. This second fixed length packet can be used for the transmission of control maintenance information and becomes effective for improving the performance of the communication equipment.