| 摘要 |
A track and hold circuit including an input terminal VIN, a first node, a second node and a capacitor CH. A diode D connects between the first node and the input terminal VH. Circuitry coupled to the first node makes the diode conductive during track mode of operation, indicated by a clock CK being at a first state, and non-conductive during hold mode of operation, indicated by a clock CK being at a second state. A transistor Q3 is coupled between said first node and said second node. The capacitor CH is connected to said second node. The transistor Q3 is operative to charge the capacitor CH during track mode and to isolate the capacitor CH from the input terminal VIN during hold mode. Additional circuitry coupled to said transistor Q3 senses the clock shifting from said first to said second state to rapidly discharge the inherent base/emitter capacitor of the transistor Q3 to thereby cause rapid turn off of the transistor Q3.
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