| 摘要 |
PURPOSE: To provide a data detection circuit capable of being used in a high- speed system and realizing low power by providing a charging means for performing the precharge of an output node based on precharge generation signals and a discharging means for performing the discharge of the output node based on the result data of a macro block. CONSTITUTION: Registers 102 and 103 for holding input data A and B are connected to the input side of the adder 1 of this semiconductor circuit. Further, the output side of the adder 1 is connected to the register 104 for holding an added result S and this data detection circuit 2 of a precharge type and an F/F 106 is connected to the output side of the data detection circuit 2. Then, based on the inversion signals COUT1 of the precharge generation signals passed through a pseudo circuit provided with delay equal to the critical pass of the adder 1, the precharge of the output node of the data detection circuit 2 is performed, the precharge is ended simultaneously with the end of an arithmetic operation, the added result S is fetched to the data detection circuit 2 and the detection operation of data is performed. |
