| 摘要 |
A novel ZVS single-ended converter configuration is provided which eliminates high voltage stresses inherent in most ZVS circuits. The present invention incorporates a mechanism for passively limited all switch voltages to whatever voltage sources are present in the converter. The voltage limiting mechanism is maintained even when driving gate signals fail, thus yielding a reliable voltage clamping mechanism. In addition, the driving waveforms for the main and auxiliary switch may be essentially complementary, thus requiring a simple driving circuit. The invention is controlled by varying the switching frequency of the switches while maintaining a constant duty cycle for each switch.
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