发明名称 TERABIT PER SECOND PACKET SWITCH
摘要 A physically realizable one terabit or more ATM packet switch 10 A that has a large number of input interfaces connected to a single stage switching fabric 14A which is in turn connected to a number of output modules 160-16 m, accordingto the generic growable packet switch architecture. This ATM packet switch 10 A is different from other growable packet switches in that it has a single stage switch fabric (14A or 14B) controlled by an out-of-band controller 20, yet it has significantly reduced complexity with respect to comparably sized electronic crossbar switches or their isomorphs. This ATM packet switch architecture is so flexible, it can be extended to provide variable length packets, circuit switched connections and fault tolerant redundant circuits using the same switch fabric and out-of-band controller architectures.
申请公布号 CA2162939(A1) 申请公布日期 1996.07.01
申请号 CA19952162939 申请日期 1995.11.15
申请人 AT&T 发明人 CLOONAN, THOMAS JAY;RICHARDS, GAYLORD WARNER
分类号 H04Q3/545;H04L12/56;H04L12/64;H04M3/00;H04Q3/00;H04Q11/04;(IPC1-7):H04L12/56 主分类号 H04Q3/545
代理机构 代理人
主权项
地址