| 摘要 |
<p>A CMOS output buffer circuit includes negative feedback means for significantly reducing voltage oscillation. The buffer circuit is comprised of a pull-up transistor (P1), a pull-down transistor (N1), a first reference voltage generator circuit (44), a second reference voltage generator circuit (54), a first negative feedback circuit (48), and a second negative feedback circuit (58). First and second negative feedback circuits are coupled between the internal power supply potential/ground potential nodes and the gates of the pull-up/pull-down driver transistors so as to reduce the rate of change of the transient charging/discharging currents, respectively.</p> |
