发明名称 |
A CACHE SRAM CONNECTOR ASSEMBLY |
摘要 |
A cache SRAM connector assembly (26) comprising a connector (28), a number of latches (30A-30B) and a number of high performance switches (32A-32C), is provided to a computer system (10). The connector (28) removably connects either asynchronous or burst cache SRAM to a processor bus (20). The latches (30A-30B) store cache access addresses being driven on a number of address lines of the processor bus (20). The high performance switches (32A-32C) being coupled to both the latches (30A-30B) and the address lines of the processor bus (20) selectively provide the cache SRAM with latched access addresses as required by asynchronous cache SRAM or directly driven access addresses on the processor bus (20) as required by burst cache SRAM.
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申请公布号 |
WO9619818(A1) |
申请公布日期 |
1996.06.27 |
申请号 |
WO1995US16487 |
申请日期 |
1995.12.18 |
申请人 |
INTEL CORPORATION |
发明人 |
MUNCE, GEORGE, R.;WARREN, JAMES, D. |
分类号 |
G06F12/08;(IPC1-7):H01J13/00;G06F12/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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