| 摘要 |
In accordance with an embodiment of the invention, a data converter (e.g., 720, 84, 78) is disclosed that provides a sampling rate conversion. The converter receives a clock signal (e.g., CKOS, CKL1, CPD or CPI), a divided-down clock signal (e.g., CKM1, CKL1, CKL2, CPDM2, or CPIL3), and first digital signal samples at a first rate. The converter converts the first digital signal samples to second digital signal samples at a second rate. The ratio of the first rate to the second rate is defined as a fist conversion rate factor. In an alternate embodiment, another stage of sampling rate conversion is provided by a second data converter. The second converter receives the divided-down clock signal, a further divided-down clock signal, and the second digital signal samples. The second data converter converts the second digital signal samples to the third rate. The ratio of the second rate to the third rate is defined as a second conversion rate factor. A second programmable counter receives the divided down clock signal and divides it down to produce a further divided-down clock signal. The second programmable counter is programmable to selectively determine the second conversion rate factor. <IMAGE> |
