| 摘要 |
a variable length decoder (VLD) (10) which operates the variable length decoding of the variable length decoded data including SSC and SVP on the ground of hold signal (HOLD), and outputs the variable length decoded data and the detecting signal of the slice start code (SSC); a run length decoder (RLD) (140) which generates the enabling hold signal (EN_HOLD = H,L) and the error generating signal (ERRPR_SVP = H) and the error rate generating signal (ERROR_SVP = L), and executes zero padding operation and releases the operation; a maintenance control block (130) which provides the clock signal inputted from an external block to VLD (10) as HOLD signal in the case of receiving ERRPR_SVP = H signal, and provides the clock signal determined according to the EN_HOLD signal to VLD (10) as HOLD signal in the case of receiving ERROR_SVP = L signal.
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