发明名称 Fast indirect antenna control
摘要 A digital interface and control module and a multi-function digital bus for use in a wireless radio frequency receiver, transmitter, or transceiver that communicates over a millimeter-wave band at multi-gigabit speeds. The control module provides a low power, low cost, small form factor, and low pin-count solution for high-speed control of a multi-gigabit radio frequency circuitry. The control module may be used to steer an antenna array for beamforming including selecting different antennas and different phases in compliance with IEEE 802.11ad/WiGig specifications. The control module may also be used for individually controlling variable gain amplifiers and low noise amplifiers and for phase shift controls, gain settings, and other controls.
申请公布号 US9450620(B1) 申请公布日期 2016.09.20
申请号 US201514749892 申请日期 2015.06.25
申请人 Nitero Pty Ltd. 发明人 Ahmed Sebastian;Richmond, II Richard Steven
分类号 H04B7/00;H04B1/00;H01Q3/24;H01Q3/36 主分类号 H04B7/00
代理机构 Hickman Palermo Becker Bingham LLP 代理人 Hickman Palermo Becker Bingham LLP ;Stone Adam C.
主权项 1. An integrated circuit for a multi-gigabit wireless communications device, the integrated circuit comprising: a memory for storing a plurality of radio frequency antenna control vectors, each of the plurality of radio frequency antenna control vectors having a bit-length; wherein the bit-length of each of the plurality of radio frequency antenna control vectors is greater than the number of the plurality of radio frequency antenna control vectors stored in the memory; a first latch connected to the memory via a first data path, the first data path having a bit-width, the number of the plurality of radio frequency antenna control vectors stored in the memory equal to two to the power of the bit-width of the first data path; a first latch enable pin connected to the first latch, the first latch enable pin operative to receive a latch enable signal and the first latch operative to close at a rising edge of the latch enable signal; a plurality of data pins connected to the first latch, the number of the plurality of data pins equal to the bit-width of the first data path, said plurality of data pins operative to receive an index that selects one of the plurality of radio frequency antenna control vectors stored in the memory; and said memory operative to receive the index from the first latch and output the selected radio frequency antenna control vector from the memory responsive to the first latch closing at the rising edge of the latch enable signal.
地址 Fitzroy, Victoria AU