forming a first conducting layer (26); forming a first epilayer (28) over the first conducting layer; forming a first pattern (29) which is confined in the unit of cell and is composed of the first epilayer (28); patterning a storage electrode (27) by etching the first conducting layer properly using the first pattern as mask; forming a second pattern (31) by etching the edge of the first pattern; forming a second epilayer; forming a spacer (30) in the side wall of the second pattern and the storage electrode pattern; removing the second pattern; etching the whole wafer anisotropically using the spacer (30) as mask.
申请公布号
KR960008527(B1)
申请公布日期
1996.06.26
申请号
KR19920025920
申请日期
1992.12.29
申请人
SAMSUNG ELECTRONICS CO., LTD.
发明人
LEE, JUNG - KIL;SHIN, CHOL - HO;HAN, DONG - HWA;NAM, INN - HO;LEE, WON - WOO