| 摘要 |
a first AND gate (20) which receives the signals (/PONRST, /MRST); an oscillator (21) which generates pulse by receiving the output of the first AND gate (20); a first OR gate (24) which receives the inverted signal (EI bar) and the obstacle signal (FLT); a second OR gate (22) which outputs the relay control signal by receiving the output signals of the oscillator and the first AND gate; a second inverter (25) which outputs the obstacle state signal (SO); a second AND gate (26) which receives the signals (SI, /MRST); a third AND gate (27) which outputs the operation state signal (EO) by receiving the output signals of the first OR gate (24) and the second AND gate (26).
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