| 摘要 |
In a semiconductor memory device of a multiple-output port type including a plurality of read buses, data in a write bus are sequentially written into write registers, and the thus written data are transferred to the even-numbered bit-line pairs of a memory cell array section, and then data are again written into the write registers, after which the thus written data are transferred to the odd-numbered bit-line pairs. Then, the data in the even-numbered bit-line pairs are transferred to read A registers which correspond to one of the read buses, and the thus transferred data are sequentially read into the read bus, and thereafter, the data in the odd-numbered bit-line pairs are transferred to the read A registers and the thus transferred data are sequentially read into the read bus. Thus, the total number of read registers corresponding to all the read buses is made equal to that of the bit-line pairs, and is accordingly smaller as compared with a conventional semiconductor memory device. This allows all the read registers to be aligned along the same lane, so that the entire memory chip can be made smaller in size.
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