CLOCK SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE

摘要

PURPOSE: To attain the same operation as that secured in a fast operation mode by giving the delay to the output signal of a selector so as to eliminate the phase difference between a reference clock signal and a clock signal that passed through a circuit that receives the supply of a clock and then generating a clock signal. CONSTITUTION: A DLL circuit 2 consists of a phase comparator 2a, a loop filter 2b and a delay line circuit 2c. The comparator 2a detects the phase difference between a reference clock signal C supplied from the outside and an internal clock signal C' that passed through an LSI internal circuit 3. The filter 2b changes the output voltage in response to the phase difference output of the comparator 2a. The circuit 2c changes the delay against the output signal of a selector 1 in response to the output voltage of the filter 2b. At the same time, the output signal of the selector 1 is supplied to a register 4 placed at a point near the output side of the selector 1 in an LSI. Then the signal C' having a phase advanced more than the output signal of the selector 1 is supplied to a register 5 placed at a point far away from the output side of the selector 1.