| 摘要 |
A testing apparatus for testing and handling a multiplicity of devices, in particular electronic components such as integrated circuits or boards, comprises a test executor with a multiplicity of hierarchical operating levels assigned to respective physical or logical entities. At each level except the lowest one, test level controllers are provided which include a pre-activity sequence of tasks, a call to a lower operating level, a return from said lower operating level, and a post-activity sequence of tasks. At the lowest level, device test processors execute the actual test.
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