BIT LINE SELECTIVE LINE STRESS CIRCUIT

摘要

PURPOSE: To shorten a screening time in an EEPROM. CONSTITUTION: When a memory cell 10 is selected, and the data are written, an NAND circuit 1, the NAND circuit 2, a NOR circuit 3, an inverter 11 and an NMOS 5 make potential of a bit line BL an 'L', and make the potential of a selective line SL an 'H' according to levels of plural signals DIN, ZNB, STRB. When the screening after write is performed, the potential of the selective line SL is made the 'H'. At this time, the output of the inverter 11 setting the potential of the bit line is made high impedance by the signal STRB inputted to the NMOS 11c, and the NMOS 12 to whose gate the signal STRHV is inputted becomes an on state. Thus, the bit line BL and the selective line SL are short-circuited, and the potential of the bit line BL becomes equal to the potential of the selective line SL.