| 摘要 |
A process of fabricating the storage capacitor for a dynamic random access memory cell which includes a transistor with gate electrode and source/drain regions on a surface of a substrate. The process forms a polysilicon layer which is coupled to one of the source/drain regions, over the transistor structure. A mask is formed to cover the planned capacitor area, and then the non-masked portion of the polysilicon layer is removed. Liquid phase deposition oxide is formed on the area not masked by the mask, and then the mask is stripped. A polysilicon sidewall spacer is formed on the sidewalls of the LPD oxide, and connects with the remaining polysilicon layer to jointly form a first capacitor electrode. The LPD oxide is removed, followed by forming a dielectric layer along the surface of the first capacitor electrode. A second capacitor electrode made from polysilicon is formed along the surface of the dielectric layer to complete the storage capacitor structure.
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