发明名称 METHOD FOR TESTING LOGIC CIRCUIT BOARD
摘要 PURPOSE: To reduce the number of the contact termianls required for a testing jig, and at the same time, to test also the function of a logic circuit board, in the testing method for the logic circuit board where the logic circuit board is tested by composing a testing circuit by mounting the testing jig on a logic circuit board to be tested. CONSTITUTION: A logic circuit board 3A to be a tested object is composed by combining a unit function block CB1 having a function, etc. The output circuit of the unit function block is made a circuit where the interruption from a circuit is functionally possible or a 3-state buffer, for instance. As for a testing, after the output circuit BF1 and BF2 of a unit function block CBF1 outputting a signal to a unit function block to be tested CB1 are made into high impedance, a signal OSB for testing from a testing device 1A is outputted to the input terminal of the unit function block CB1 via the contact termians CI1 and CI2 of a testing jig 2A, test result signals ISB are inputted from contact terminals CO1 and CO2, and the property of the unit function block CB1 is decided from the inputted result.
申请公布号 JPH08166893(A) 申请公布日期 1996.06.25
申请号 JP19940311441 申请日期 1994.12.15
申请人 FUJI ELECTRIC CO LTD;FUJI FACOM CORP 发明人 INOUE TAKESHI
分类号 G06F11/22 主分类号 G06F11/22
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