| 摘要 |
An improved access right checking apparatus is provided which has a selector permitting high speed access right checking in a different execution level than a processor current execution level. The selector may select either a processor current execution level or an execution level in which access rights are checked. Information of the access right checking request including the execution level is transmitted through a data bus to a decoder, after which the information is decoded and fetched as a selective signal. The selective signal is applied to the selector. When the access right checking performance is requested, the selector permits the processor current execution level to be temporarily switched into a predetermined execution level in which the access rights are checked.
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