发明名称 THREE-INPUT ARITHMETIC AND LOGIC UNIT FOR FORMATION OF SUM OF FIRST BOOLEAN COMBINATION OF SECOND INPUT AND THIRD INPUTADDED TO FIRST INPUT PLUS SECOND BOOLEAN COMBINATION OF SECOND INPUT AND THIRD INPUT
摘要 PURPOSE: To provide a three-input arithmetic logical device for forming the arithmetics of three multi-bit input signals and a boolean mixing combination. CONSTITUTION: An arithmetic logical device forms a Boolean combination at first and, then, forms an arithmetic combinaton. A present instruction drives an instruction decoder which generates function signals F0-F7 for controlling the formed comhinations. It is favorable that the aggregation of bit circuits is used in the three-input arithmetic logical device 230 and the respective bit circuit s form carry propagation generation and killing signals. The signals are used together with a multi-level logical tree circuit and a carry input so that a bit result and a carry output to the succeeding bit circuit are generated. This structure attains forming the arithmetic, Boolean or arithmetic and Boolean mixing function where the three input signals are selected based on the present instruction. A function signal is selected so as to permit the combination not to respond to one of the input signals and the two input functions of the residual input signals are executed.
申请公布号 JPH08161460(A) 申请公布日期 1996.06.21
申请号 JP19940296708 申请日期 1994.11.30
申请人 TEXAS INSTR INC <TI> 发明人 KAARU EMU GUTSUTAGU;RICHIYAADO SHINPUSON;BURENDAN UORUSHIYU
分类号 G06F7/509;G06F7/50;G06T1/00;G06T1/20;G06T11/00;(IPC1-7):G06T1/00 主分类号 G06F7/509
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