发明名称 METHOD AND APPARTUS FOR EXECUTION AND PROTECTION OF LINEAR SEQUENCE OF INSTRUCTION PROCESSED BY PROCESSOR
摘要 PROBLEM TO BE SOLVED: To detect an execution error in the linear order of commands which are processed by a processor and stored in prescribed start addresses in a memory. SOLUTION: At the time of writing, respective words in a sequence 10 are made to correspond to one bit from a start address word, a bit that is not used in the respective word in the sequence, which are to be written, is decided so that the value of the corresponding bit of the start address word becomes equal to the result of a prescribed function applied to the bit of the word. At the time of reading, the result of the function applied to the bit of the word which is read is compared with the value of the corresponding bit of the start address word. When a difference exists, an error signal is transmitted.
申请公布号 JPH08161234(A) 申请公布日期 1996.06.21
申请号 JP19950191346 申请日期 1995.07.27
申请人 SEXTANT ABUIONIIKU 发明人 PITO KURISUCHIYAN;MARUTEINE MISHIERU
分类号 G06F12/16;G06F11/10;G06F11/28;(IPC1-7):G06F12/16 主分类号 G06F12/16
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