| 摘要 |
PURPOSE: To suppress a wonder between reference clock pulses and output clock pulses by using a counter circuit and a reference voltage control circuit, controlling the reference voltage of an amplifier and suppressing the fluctuation of a stationary phase error small. CONSTITUTION: The counter circuit 10 is connected to an input terminal 1, an N frequency divider circuit 8 and a voltage controlled oscillation circuit 7. Then, the counter circuit 10 counts the output clock pulses S2 of a frequency N.f0 between the change point of the frequency fs of the reference clock pulses S1 and the change point of the frequency f0 of frequency division clock pulses S3 and outputs the counted result S4 to the reference voltage control circuit 11. The circuit 11 is connected between the circuit 10 and the reference voltage generation circuit 9 of the amplifier 6. The circuit 11 integrates a count number indicated by the counted result S4 for the time sufficiently longer than the time constant of a PLL loop, compares an integrated result with the count number (p) in a normal state and controls the reference voltage of the circuit 9 corresponding to the direction and size of the difference of the count numbers. |
