CLOCK SUPPLYING METHOD FOR SHIFT REGISTER CIRCUIT, CLOCKED INVERTER AND SHIFT REGISTER CIRCUIT

摘要

PURPOSE: To obtain a shift register having no malfunction. CONSTITUTION: A first holding means D1 including a clocked inverter circuit CI1 operating with a first clock signal C1 and a second holding means D2 including a clocked inverter circuit CI3 operating with a second clock signal C2 being the inversion signal of the first clock signal C1 are alternately directly connected so that the output terminal of the holding means of the prestage is connected to the input terminal of the holding means of the poststage. In this shift register circuit 100, an overlapping period T1 is adjusted so that the relationship between the overlapping period T1 in which the first clock signal C1 and the second clock signal C2 simultaneously become a prescribed logic level and the propagation delay time to per one stage of the holding means satisfy the relationship being T1