| 摘要 |
first and second NAND gates(G1,G2) for driving writing action by receiving data input of positive/negative signals through terminals(/D, D) and a write enable signal through other terminal(WE); and first and second MOS transistors(Q30, Q40) for precharging the data bus line in reading action, and providing a path in writing action by keep being turned on to form a channel between output terminals of the NAND gates(G1,G2) and data bus lines(DB, /DB); thereby reducing the number of elements and power consumption.
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