发明名称 METHOD AND DEVICE FOR TESTING WIRING ON SEMICONDUCTOR INTEGRATED CIRCUIT CHIP
摘要 PURPOSE: To observe the conducted state of wiring on an IC chip by scanning an area to be scanned on the IC with a radiant beam and detecting current variation at each scanning point. CONSTITUTION: After the area to be observed of a sample 6 is moved to the irradiating extent with a laser beam 5 by means of a sample stage 7, electric power is supplied from a power source 8. Then, the area to be observed is digitally scanned by irradiating the area with the beam 5. The staying time of the beam 5 at each scanning point in the area is set at 2μsec. A current variation detecting section 9 converts the current variation at each point within the staying time into a voltage after averaging the current variation and stores the voltage at the address in a memory corresponding to the coordinates of each scanning point after A/D-converting the voltage. When the scanning of the whole area is completed, the section 9 informs an image displaying section 10 of the completion. The section 10 reads out voltage values from the addresses in the memory corresponding to each scanning point, converts the voltage values into luminance information, and displays the information at 256 levels at each point on a CRT screen corresponding to each scanning point. Therefore, the electric current flowing through wiring of an IC can be observed.
申请公布号 JPH08160095(A) 申请公布日期 1996.06.21
申请号 JP19950025758 申请日期 1995.02.15
申请人 NEC CORP 发明人 FUTAGAWA KIYOSHI
分类号 G01R31/26;G01R31/02;G01R31/302;G01R31/303;G01R31/307;G01R31/311;H01L21/66;(IPC1-7):G01R31/02 主分类号 G01R31/26
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