| 摘要 |
<p>PURPOSE: To detect the data input break with higher stability in a simple constitution and without using any data clock. CONSTITUTION: A timing generation circuit 2 generates a synchronous pattern detection timing signal which is kept at an 'H' level for an 'H' level period of the reference clock that is set in response to the 1st and 2nd rises of a reference clock (having 1/3N frequency of a data clock) which is acquired after the rise of a frame pulse and also generates an input break detection timing signal that rises synchronously with the 3rd rise of the reference clock. A synchronous pattern identification circuit 11 detects a prescribed synchronous pattern out of the data synchronously with the synchronous pattern detection timing signal. A counter 12 detects the break of data based on the detection result of the circuit 11 and at the same time outputs an input break detection signal synchronously with the input break detection timing signal.</p> |
