发明名称 METHOD FOR TESTING ERROR CORRECTION CIRCUIT AND ERROR CORRECTION LSI AUTOMATIC TESTING DEVICE
摘要 PURPOSE: To simplify the test of an error correction circuit and to reduce decision errors by comparing the dynamic measured value (statistic amount) of the error correction capacity of a circuit to be tested and the reference value of the error correction capacity determined by a numerial calculation. CONSTITUTION: An exclusive OR circuit 7 takes an exclusive OR of the cord word string outputted from a cord word generation circuit 5 and the error pattern string outputted from an error source circuit 6, defines the cord word string in which an error is fetched as a test signal and supplies the test signal to a first counter circuit 8 and a circuit 13 to be tested. A comparison decision circuit 11 checks whether the total number S1 of cord word outputted from the circuit 8, the total number S2 of corrected word outputted from a second counter circuit 9 and the reference value R outputted from a reference value calculation circuit 10 satisfy|(S2 /S1 )-R|<=ε, for all the errors or not.εis defined as a preliminarily set allowable value. When this expression is satisfied, it is decided that the circuit 13 is good. When the expression is not satisfied, it is decided that the circuit 13 is not good. This decision result is supplied to a decision output terminal 12 and is outputted to the outside.
申请公布号 JPH08162978(A) 申请公布日期 1996.06.21
申请号 JP19940306287 申请日期 1994.12.09
申请人 NIPPON HOSO KYOKAI <NHK> 发明人 KOBAYASHI KAZUMASA;KOBAYASHI KIICHI;KOKUBU HIDEKI;YAMANO KOJI
分类号 G01R31/28;G06F11/08;G06F17/50;H03M13/00;H03M13/01;(IPC1-7):H03M13/00 主分类号 G01R31/28
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