NOISE CHARACTERISTICS ENHANCEMENT CIRCUIT OF SEMICONDUCTOR ELEMENT

摘要

an inverting means comprising a first PMOS transistor and an NMOS transistor connected in series; a second PMOS transistor connected between an inverted pull-up transistor and the voltage source; a delaying means delaying the logic state outputted from the inverting means; and a latch means preventing the output state of being floating at the high potential state in case of the low state of input logic signal. The delay circuit output controls the gate of the second PMOS transistor.