| 摘要 |
<p>A circuit for serializing n parallel data bits (D1-D4) requires that the data clock (CLK), having a clock period T, be used to generate n phased clocks of the same frequency as the data clock, but varying in phase such that each phased clock is delayed T/n with respect to the previous one. This can be done using a digital phase locked loop device (17). These n phased clocks and n parallel data bits are then input to a logic circuit which uses an n input Register (16) and an n input multiplexer (22) to output one data bit (d1-d4) for each phased clock. The result is a serializer that converts parallel data to serial data without the need for generating a higher frequency clock. <IMAGE></p> |
