| 摘要 |
The circuit is for increasing the speed of the mode selection capability of SP, LP, and EP for video. A control pulse(CTL) recorded on the video tape is fed into the circuit and delayed by a first inverter and a condenser. The delayed control pulse is delayed again through a lowpass filter. An output from the lowpass filter is applied to a second, a fourth, and a sixth inverter each having different threshold voltage. The second inverter having the lowest threshold voltage detects EP, LP, and SP as the lowpass filtered control pulse reaches to the threshold voltage of the second inverter.
|
