发明名称
摘要 <p>PURPOSE:To reduce the software load by using an arithmetic circuit set into a timer to perform the conditional control of comparison and arithmetic against the value of a timer set into the timer. CONSTITUTION:A programmable interval timer consists of a data bus buffer 4, a control circuit 5, an internal data bus, etc., together with a counter 1, a register 2, and an arithmetic circuit 3 which performs comparison/arithmetic between the counter 1 and the register 2. When the new data is written into the register 2 during a count-down operation of the timer, the value of this new data is compared with the present counter value. Then a count-down operation is newly carried out with the smaller value decided by said comparison defined as the initial value. The register 2 is set in a mode where the data differential is held. Thus it is not required to stop the count-down operation during the read/write operations of the register 2. Then the timer stop time is minimized.</p>
申请公布号 JP2508026(B2) 申请公布日期 1996.06.19
申请号 JP19860250123 申请日期 1986.10.20
申请人 MITSUBISHI ELECTRIC CORP 发明人 NAKADA KYOSHI;TSUBOTA HIDEO
分类号 G06F1/14;G06F1/00;(IPC1-7):G06F1/14 主分类号 G06F1/14
代理机构 代理人
主权项
地址