| 摘要 |
<p>PURPOSE:To reduce a erasure time by providing a sense amplifier revising read sensitivity at erasure verification so as to discriminate it to be in the erasure state when a current flows to all connected bit lines and providing a Y decoder whose plural bit lines are connected to the sense amplifier simultaneously at the erasure verify. CONSTITUTION:Since a signal ER reaches an L level in the entry to the erasure verification, all Y gate lines 9 - 11 go to an H level by NAND gates 35 - 37 of a Y decoder 21 and Y gates 12 - 14 are turned on. Simultaneously, a Z gate 23 is selected by a Z decoder 22 and all bit lines 4 - 6 connected to the Z gate 23 are connected to a sense amplifier 25. A signal ER goes to L in the sense amplifier 25 and a P-channel transistor (TR) 39 is turned on, even when the number of bit lines to be sensed is increased, the data is read with the sensitivity of sense similar to that with one bit line. Thus, the erasure verification is quickened and the erasure time is also reduced.</p> |
