发明名称 Semiconductor memory device
摘要 <p>A semiconductor device is constituted by a booster circuit, memory cell arrays (MCA1, MCA2), a sense amplifier circuit (S/A), transmission gate circuits (Q4, Q5; Q9, Q10), equalizing circuits (Q1, Q2, Q3; Q6, Q7, Q8) and a control circuit applying a boosted potential respectively to the gates of MOS transistors of the transmission gate circuits and the equalizing circuits when no memory cells of the memory cell arrays are selected whereby the capacitance of de-coupling capacitors connected to output terminals of the booster circuit can be reduced thereby contributing to reduction in chip area. &lt;IMAGE&gt;</p>
申请公布号 EP0717415(A2) 申请公布日期 1996.06.19
申请号 EP19950118297 申请日期 1995.11.21
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KANEKO, TETSUYA
分类号 G11C11/407;G11C5/14;G11C11/401;G11C11/408;G11C11/409;G11C11/4091;(IPC1-7):G11C11/409 主分类号 G11C11/407
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