| 摘要 |
PURPOSE:To attain interfacing between a high speed serial data and a low speed parallel data under the use of a low speed small capacity memory circuit by applying the processing for the speed conversion to serial/parallel or parallel/ serial system as to a data being the result of conversion of a serial data into a parallel data or a parallel data. CONSTITUTION:A serial data composing of m-set of serial data groups is subject to speed conversion by a sped conversion circuit applying m-phase 1st prescribed parallel data and outputted as the m-phase parallel data. Then the data is converted into a new m-phase parallel data in a selector circuit 11. The new m-phase parallel data is stored in a memory circuit corresponding to each phase and the rearranged m-phase parallel data are outputted from m-set of memory circuits 121-12m. Then the data are formed into parallel m-set data groups by a selector circuit 13 and then outputted. |
