| 摘要 |
A data, synchronization device adapted to re-synchronize a multi-level digital signal (IN; OUT) with an output or local clock signal (CLKO). In case of a binary signal, the device includes two counter systems (CA1-CC1, MAJ1, SEL1; CA0-CC0, MAJ0, SEL0) each associated with a logical level of the signal and counting the number of successive 1's or 0's respectively. These counter systems produce a count number including the number of counted bits and their level. The device further includes a decoder (DEC) generating in synchronism with the local clock signal (CLKO) a number of bits which is a function of the count numbers. These generated bits constitute the requested output signal (OUT). The data synchronization device further includes delay module (DEL) for deriving from an input clock signal (CLKI) received with the input signal (IN), three intermediate clock signals (OA-OC) shifted in phase with respect to each other and each controlling one of a set of three counters (CA1-CC1; CA0-CC0) included in each of the counter systems. The latter also each include a majority voting module (MAJ1; MAJ0) reading the numbers of bits counted by the three counters of the corresponding set, comparing these numbers and selecting the subset of at least two counters having counted a same number of bits. The number of bits counted by the majority of the set counters is assumed to be correct and is therefore transferred to the decoder (DEC).
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