| 摘要 |
Any one of several improved devices capable of implementing microwave phase logic (MPL) operating at gigabits per second rates comprises either at least one of means performing the function of a multigate microwave-monolithic-integrated-circuit (MMIC) field-effect transistor (FET), or a pair of doubly-balanced mixers, in which each of the mixers includes an RF port, a local-oscillator (LO) port and an IF port, and the IF port of a first of the doubly-balanced mixers is directly connected to the IF port of a second of the doubly-balanced mixers. The first of the doubly-balanced mixers is operative as a demodulator for deriving (1) a given polarity at its IF port in response to substantially in-phase signals of the same first specified frequency being respectively applied to its RF and LO ports and (2) a polarity opposite to the given polarity at its IF port in response to substantially out-of-phase signals of the same first specified frequency being respectively applied to its RF and LO ports, and the second of the doubly-balanced mixers is operative as a modulator for deriving (3) a signal of a given phase and second specified frequency at its RF port in response to a signal of the second specified frequency being applied to its LO port and the given polarity being applied its IF port and (4) a signal of a phase substantially 180 DEG out-of-phase with the given phase and second specified frequency at its RF port in response to a signal of the second specified frequency applied to its LO port and the polarity opposite to the given polarity being applied its IF port.
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