Charge shared precharge scheme to reduce compare output delays

摘要

The charge shared precharge circuit of the present invention is coupled to the match line. The precharge circuit is disposed between the match line and a match line, and includes a CMOS passgate having an N channel and a P channel gate. An inverter acts as a match driver and is coupled between the match and match lines at the CMOS passgate's input and output. The input to the N channel gate of the pass gate is coupled through an inverter to the input of the P channel gate. The N channel gate is further coupled to Vcc through two serially coupled P channel transistors receive BEQ line and an SAE signal, respectively. At the beginning of a compare cycle, BEQ is driven low as is SAE, thereby turning on the serially coupled P channel transistors and coupling Vcc to the input of the N channel gate of the passgate. The P channel gate of the passgate is also opened due to the placement of the inverter between the N and P channel gates. The passgate is thereby turned on and current passes through the passgate between the match and match lines. The opening of the passgate and the coupling of the inverter between the match and match lines, results in a shorting of Vcc to ground. The shorting of Vcc to ground results in a voltage precharge of the match line to Vcc/2. After a predetermined precharge time, the SAE signal is driven high thereby turning off the P channel transistor, and electrically decoupling Vcc from the gates of the CMOS passgate and the match line. The compare circuit of the present invention then compares the bits of word A with word B, as described herein.