Semiconductor memory error-bit safeguard device for dynamic random access memory

摘要

The device includes a matrix (19) of storage cells arranged in X and Y directions, an address memory device (11), and an address generating device (16). The address memory device stores at least the X-address of error-bit storage cells of the cell matrix. The error bit storage cells are defined by the X- and Y-address in the storage cells matrix. The address generating device generates an address Xe + m, m being a positive or negative integer. This generated address acts as an internal address if the X-address Xe corresp. to the error bit address of an external section is given.