发明名称 Synchronizing circuit
摘要 <p>Three signal samples (A25, C26, B27) of a digital signal DATA are taken simultaneously in three different time positions (t25, t26, t27) of this signal and separated by a small time interval (T). As long as the three signal samples are equal it may be deduced therefrom that the three time positions occur within the duration of a same data bit of DATA and a new set of three time positions (t24, t26, t28) of which the time interval separating them is increased is then taken, the latter set being thus "expanded" over a larger region of this data bit. If, on the contrary, a signal sample (B28) is different from the two others (A24, C26) it may be deduced therefrom that only two time positions (t24, t26) occur within the duration of a data bit. A new set of three time positions (t24, t25, t26) is then taken with the initial small time interval (T) and with the new medium time position shifted over this time interval (T) to the left or to the right depending on which of the signals samples is different from the others. If the three signal samples (A24, C25, B26) taken in the three new time positions are then equal, the above process is repeated. In conclusion, when the "largest" set of time positions (t12, t20, t28) is obtained, the medium time position thereof (t20) always occurs in the middle of a data bit and the signal sample (C20) taken in this medium time position is optimum for representing this data bit and for generating another digital signal synchronized with the clock signal CLOCK. <IMAGE></p>
申请公布号 EP0502260(B1) 申请公布日期 1996.06.12
申请号 EP19910200475 申请日期 1991.03.05
申请人 ALCATEL BELL NAAMLOZE VENNOOTSCHAP 发明人 SEVENHANS, JOANNES MATHILDA JOSEPHUS;SCHMIT, JEAN-JACQUES
分类号 H04L7/033;(IPC1-7):H04L7/033 主分类号 H04L7/033
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