发明名称
摘要 PURPOSE:To attain high speed for a logical gate and low power consumption by constituting transistors (TRs) of the logical gate so that no branch point exists in a path from a power supply to an output terminal of the logical gate. CONSTITUTION:N-channel MOS TRs 1-4 and P-channel MOS TRs 5-7 are used. A series element comprising the TR 1 whose gate receives an input signal A and the TR 2 whose gate receives an input signal C and a series element comprising the TR 3 receiving an input signal B at the gate and the TR 4 receiving the signal C at the gate are connected in parallel to form the 1st parallel element. A series element comprising the TR 5 receiving the signal A at the gate and the TR 6 receiving the signal B at the gate, and the TR 7 receiving the signal C at the gate are connected in parallel to form the 2nd parallel element. One terminal of the 1st parallel element is connected to a voltage point GND and one terminal of the 2nd parallel element is connected to a voltage point VDD, the other terminals of both the parallel elements are connected for the output terminal. Through the constitution above, high speed logical gate and low power consumption are attained.
申请公布号 JP2506636(B2) 申请公布日期 1996.06.12
申请号 JP19850150728 申请日期 1985.07.09
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 UYA MASARU;KANEKO KATSUYUKI;NISHIMICHI YOSHIHITO
分类号 H01L27/092;H01L21/8234;H01L21/8238;H01L27/088;H03K19/094;H03K19/0948;H03K19/0952;H03K19/20;(IPC1-7):H03K19/094;H01L21/823 主分类号 H01L27/092
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