| 摘要 |
A cache line replacing apparatus for use in a computer system having a central processing unit (CPU), a main memory and a cache memory, in which a cache line information of a CPU/cache bus is written-back into the main memory, and desired cache line information is read from the main memory to a memory bus to transmit the read cache line information to the CPU/cache bus, the cache line replacing apparatus including a first storage unit in which write-back data of the CPU/cache bus is stored, a second storage unit in which data which is read from the main memory to the memory bus is stored, a register for increasing a count value thereof when data is stored in the second storage means and decreasing the count value when the data is read from the second storage means, and a multiplexer for selectively transmitting the data stored in the second storage means to the CPU/cache bus or transmitting the data of the memory bus to the CPU/cache bus, according to the count value of the register. Accordingly, the time delay due to the write-back buffering can be avoided and the CPU can read the data without the loss of the memory bandwidth.
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