Single event upset immune register with fast write access

摘要

A single event upset hardened bi-stable CMOS circuit has a pair of cross coupled invertors with an isolation resistor in the path coupling the drains of the transistors in each invertor. Each invertor includes a PFET and a NFET pair coupled source to drain. An isolation resistor couples together the drains of each PFET-NFET pair and two low impedance conductive paths provide a direct coupling between the drains of each transistor of one invertor to common gate node of the other invertor.