| 摘要 |
<p>PURPOSE: To provide a nonvolatile semiconductor memory provided with an erase circuit increasing an erase speed of a memory cell and shortening an erase time and maintaining conventional performance related to the low voltage of an erasing source voltage. CONSTITUTION: The erase circuit 2 makes an erase signal ER bar and a drive voltage of a common source line VS input signals drive the common source line VS. Comparators 35 and 36 compare the drive voltage of the common source line VS with a reference voltage Vref1 or Vref2, and output a low level when the drive voltage is larger than the reference voltage. OR gates 33 and 34 make the output signal of the comparator 35 or 36 and the erase signal ER bar the input signal. PMOS transistors MP1 and MP2 which the output signals of the OR gates 33 and 34 are inputted respectively to gate electrodes, whose source electrodes is connected to the erasing source voltage Vpp and to whose drain electrodes is connected to the common source line VS and are driven in high voltage.</p> |
