发明名称 TIMING CONTROL CIRCUIT AND DELAY CIRCUIT
摘要 PURPOSE: To provide a timing control circuit by which the timing of a control signal to be used can appropriately be controlled corresponding to the period of the control signal in the timing control circuit for controlling the timing by changing the phase of a signal in an electronic circuit. CONSTITUTION: This circuit is provided with a first circuit 1 to which a control signal CLK is inputted, and having first delay time IB-1, a second circuit 2 having second delay time IB-2, and a time difference expanding circuit 3 for expanding time difference τbetween the switching timing of a first signal A passing through both the first and second circuits 1 and 2 and the switching timing of second signals B and C passing through only the first circuit 1 to be α-fold (α>=1), thereby obtaing the output to be switched with the fixed time difference from the control signal CLK.
申请公布号 JPH08152935(A) 申请公布日期 1996.06.11
申请号 JP19950246127 申请日期 1995.09.25
申请人 FUJITSU LTD 发明人 OKAJIMA YOSHINORI;YANAGAWA MIKI
分类号 G06F1/06;G11C11/407;G11C11/4076;G11C11/4093;H03K5/13;H03K5/131;H03L7/00 主分类号 G06F1/06
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