| 摘要 |
PURPOSE: To provide a PLL frequency synthesizer which contains a sample/hold phase detector, can shorten the frequency switching time, and also can improve the frequency stability. CONSTITUTION: The current generating parts 11 and 12 of different current capacities are properly switched by the control of a control part 13 based on the phase difference between a reference signal (a) and a sampling pulse signal (b) obtained by dividing the output branching cram a voltage controlled oscillator 4. Thus a lamp capacitor 3 is charged. When the phase difference is larger than a prescribed level, the capacitor 3 is charged first at the part 12 of larger current capacity so that the frequency switching time is shortened. When the phase difference is smaller than the prescribed level and the output frequency is locked, the capacitor 3 is charged first at the part 11 of smaller current capacity. Thus the frequency stability is improved. |
